The continuing and increasing demand for low power integrated circuits, particularly for more complicated battery powered, portable devices, requires that SRAM cells have good power consumption characteristics. One measure of the power consumption is the standby leakage current Isb. When the SRAM cell is not being used, the SRAM array may be placed in a standby mode. The leakage current consumed during standby, Isb, should be minimized. It is clearly advantageous to provide SRAM cells with a low Isb value. This is difficult to do reliably for the 6T storage cells, however, due to process variations and other constraints increasingly imposed by shrinking device sizes. For example, the contact material is often seen leaking to the shallow trench isolation. The overlap region between the gate and the active region causes gate leakage.
Thus, there is a continuing need for a SRAM bit cell structures that has a lower standby leakage current Isb for lower standby power and improved access speed particularly during read operations, while remaining compatible with state of the art semiconductor process for fabricating integrated circuits, without adding significant steps or significant added costs.